In accordance with an embodiment, a circuit includes a current digital-to-analog converter (DAC) having a current switching network coupled to a current DAC output, a first cascode current source coupled between a first supply node and the current switching network, a second cascode current source between a second supply node and the current switching network, and a shorting switch coupled between a first cascode node of the first cascode current source, and a second cascode node of the second cascode current source.

A rotation detector detecting rotation of a rotor, based on a signal produced according to rotation of the rotor, having a waveform according to a rotational cycle thereof, includes a signal obtaining unit to obtain two signals having phases different from each other; a vector operating unit to determine a vector according to a rotational angle of the rotor, based on the two signals; and a rotation detecting unit to detect rotation of the rotor, based on the vector. The two signals are produced from two elements located at positions farthest in a rotational angle of the rotor among plural rotation detecting elements located at positions different from each other.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

A precision bipolar digital-to-analog converter (DAC) that provides a bipolar current output having a substantially fixed zero center point is provided. The DAC includes digital-to-analog converter circuitry configured to provide, responsive to a reference signal indicative of the digital data, a first analog current signal having a first potential and a second analog current signal having a second potential, subtractor circuitry configured to provide a bipolar current signal by subtracting the second analog current signal from the first analog current signal, the bipolar current signal having a zero center point, and first control circuitry electrically coupled to the subtractor circuitry and to the digital-to-analog converter circuitry, and configured to modify the second potential so that the second potential equals the first potential.

A precision bipolar digital-to-analog converter (DAC) that provides a bipolar current output having a substantially fixed zero center point is provided. The DAC includes digital-to-analog converter circuitry configured to provide, responsive to a reference signal indicative of the digital data, a first analog current signal having a first potential and a second analog current signal having a second potential, subtractor circuitry configured to provide a bipolar current signal by subtracting the second analog current signal from the first analog current signal, the bipolar current signal having a zero center point, and first control circuitry electrically coupled to the subtractor circuitry and to the digital-to-analog converter circuitry, and configured to modify the second potential so that the second potential equals the first potential.

Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

Apparatus and methods for reducing input bias current of electronic circuits are provided herein. In certain implementations, an electronic circuit includes a first input terminal, a second input terminal, an input circuit, and a plurality of input switches including at least a first input switch and a second input switch. The first input switch is electrically connected between the first input terminal and a first input of the input circuit, the second input switch is electrically connected between the second input terminal and a second input of the input circuit, and the first and second input switches can be opened and closed using a clock signal. The electronic circuit further includes a charge compensation circuit for compensating for charge injection through the first and second input switches during transitions of the clock signal.

Improved mechanisms for applying noise-shaped segmentation techniques in a multi-bit DAC are disclosed. Noise-shaped segmentation refers to constructing two or more noise-shaped signals whose sum equals the original digital input signal by splitting each word of the input signal into two or more sub-words and converting each sub-word by a respective sub-word DAC group. Disclosed mechanisms include determining a range of amplitudes of a portion of the input signal over a certain time period, and, when converting digital words of that portion to analog values, limiting the number of sub-word DAC groups which are used for the conversion only to a number that is necessary for generating an analog output corresponding to the portion being evaluated, which number is determined based on the tracked amplitudes and could be smaller than the total number of sub-word DAC groups. Placing unused sub-word DAC groups into a power saving mode reduces power consumption.

Improved mechanisms for applying noise-shaped segmentation techniques in a multi-bit DAC are disclosed. Noise-shaped segmentation refers to constructing two or more noise-shaped signals whose sum equals the original digital input signal by splitting each word of the input signal into two or more sub-words and converting each sub-word by a respective sub-word DAC group. Disclosed mechanisms include determining a range of amplitudes of a portion of the input signal over a certain time period, and, when converting digital words of that portion to analog values, limiting the number of sub-word DAC groups which are used for the conversion only to a number that is necessary for generating an analog output corresponding to the portion being evaluated, which number is determined based on the tracked amplitudes and could be smaller than the total number of sub-word DAC groups. Placing unused sub-word DAC groups into a power saving mode reduces power consumption.

A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.