A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

A decoding device is used to securely send corresponding data gathered from multiple underground sources to multiple users. The device comprises a signal receiving port connected to multiple bandwidth filters and further connected to internet access points that are assigned to end users for secure data access. The invention facilitates allowing the signal and data being transmitted through the formation of the earth to reach end users located nearby and significant distances away from the source of the transmission. A system and method utilizing the decoding device is provided.

A decoding device is used to securely send corresponding data gathered from multiple underground sources to multiple users. The device comprises a signal receiving port connected to multiple bandwidth filters and further connected to internet access points that are assigned to end users for secure data access. The invention facilitates allowing the signal and data being transmitted through the formation of the earth to reach end users located nearby and significant distances away from the source of the transmission. A system and method utilizing the decoding device is provided.

The present invention discloses a DAC method having signal calibration mechanism. A first conversion circuit generates a first analog signal according to an input digital signal. A second conversion circuit generates a second analog signal according to the input digital signal and a pseudo-noise digital signal. An echo transmission circuit processes a signal on an echo path to generate an echo signal. A first and a second calibration circuits generate a first and a second calibration signals. A calibration parameter calculation circuit performs calculation according to a difference between the echo signal and a sum of the first and the second calibration signals and related path information to generate a first and a second offsets. The first and the second calibration circuits converge first and second response coefficients and update a first and a second codeword offset tables according to the first and the second offsets.

A circuit system for weight modulation and image recognition of a memristor array includes a personal computer (PC), a field-programmable gate array (FPGA) chip, a digital-to-analog conversion unit, a switch unit, a memristor array unit, an integration and signal amplification circuit, and an analog-to-digital converter. The circuit system selects a to-be-realized function such as array reading and writing, weight modulation or image recognition, converts a command or an RGB value of an image collected by the PC into a corresponding grayscale value, and sends the grayscale value to the FPGA chip. The FPGA chip controls and selects a to-be-modulated memristor array unit through the digital-to-analog conversion unit and the switch unit. An application program of the PC controls the FPGA chip in real time to realize array reading and writing, weight modulation, and image recognition, and then the FPGA chip displays a result on the PC in real time.

A circuit system for weight modulation and image recognition of a memristor array includes a personal computer (PC), a field-programmable gate array (FPGA) chip, a digital-to-analog conversion unit, a switch unit, a memristor array unit, an integration and signal amplification circuit, and an analog-to-digital converter. The circuit system selects a to-be-realized function such as array reading and writing, weight modulation or image recognition, converts a command or an RGB value of an image collected by the PC into a corresponding grayscale value, and sends the grayscale value to the FPGA chip. The FPGA chip controls and selects a to-be-modulated memristor array unit through the digital-to-analog conversion unit and the switch unit. An application program of the PC controls the FPGA chip in real time to realize array reading and writing, weight modulation, and image recognition, and then the FPGA chip displays a result on the PC in real time.

A control method of a switching circuit, a control circuit of the switching circuit and the switching circuit are provided. The control circuit includes a slope buffer and a first operational amplifier. The slope buffer receives a first voltage reference, and controls slopes of a rising edge and a falling edge to generate a second voltage reference. The first operational amplifier receives an output feedback voltage and a reference voltage, and performs an operational amplification to obtain a compensation voltage. When the first voltage reference has the falling edge, the reference voltage is coupled to the first voltage reference through a first switch, and the second voltage reference is coupled to an output voltage through a second switch. When the first voltage reference has the rising edge, the reference voltage is coupled to the second voltage reference through a third switch.

A control method of a switching circuit, a control circuit of the switching circuit and the switching circuit are provided. The control circuit includes a slope buffer and a first operational amplifier. The slope buffer receives a first voltage reference, and controls slopes of a rising edge and a falling edge to generate a second voltage reference. The first operational amplifier receives an output feedback voltage and a reference voltage, and performs an operational amplification to obtain a compensation voltage. When the first voltage reference has the falling edge, the reference voltage is coupled to the first voltage reference through a first switch, and the second voltage reference is coupled to an output voltage through a second switch. When the first voltage reference has the rising edge, the reference voltage is coupled to the second voltage reference through a third switch.

Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled.

Systems for monitoring or control can include reconfigurable input and output channels. Such reconfigurable channels can include as few as a single terminal and a ground pin, or such channels can include three or four terminal configuration such as for use in four-terminal resistance measurements. Channel reconfiguration can be accomplished such as using software-enabled or firmware-enabled control of channel hardware. Such channel hardware can include analog-to-digital and digital-to-analog conversion capability, including use of a digital-to-analog converter to provide field power or biasing. In an example, compensation can be provided to suppress a leakage current from flowing through a digital output to a load connected to the reconfigurable channel terminal, particularly when the digital output is disabled.